1. Field of the Invention
The present invention relates to computer memory systems and more particularly to a memory access system and method which improve the availability of memory systems comprising memorization subsystems and allow a memorization subsystem to be automatically replaced without loosing data and perturbing the computer using such memory systems.
2. Background of the Invention
In today""s computers, the memory system is generally made of a plurality of memorization subsystem cards, e.g. Dual In-line Memory Modules (DIMMs). DIMMs are built with several Synchronous Dynamic Random Access Memory (SDRAM) chips, the number of chips depending upon the DIMM memory size, the data bus width, etc. Generally, to store a data in a memorization subsystem card containing several memory chips that can store one byte words, this data is split up into bytes, the first byte is stored in a first memory chip, the second byte in a second memory chip and so on.
These memory chips are subject to different kind of failures:
soft failures that are intermittent failures due to external noisy environment, like Alpha particles, that disappear if the data word is rewritten at the failing memory location or after a memory reset.
hard failures that are permanent defects affecting a memory chip, like micro short-circuits, that remain definitively even after memory reset.
These failures, when occurring, may damage the memory system content and then disturb the correct functioning of the current application running on the computer and lead generally to stop this computer in order to replace the failing memorization subsystem card.
To get rid of these failures, Error Correcting Codes (ECC) are generally used to improve the overall memory system failure rate. Indeed, ECC have the capacity to correct automatically errors occurring in a single memory chip without disturbing the functioning of the memory system. To do that, the ECC functions write path function and read path function, that may be located inside the memory controller, are able to detect a failing word and correct it automatically thanks to ECC bits that are stored in additional memory chips on the memorization subsystem card. For example, Single Error Correction (SEC) code can correct one error in a single memory chip, Double Error Correction (DEC) code allows to correct two errors located in the same memory chip, and finally Block Error Code (BEC) code allows to correct all errors in a single memory chip. For instance, the 8-bits Block Error Code, derived from the theory of Bose-Chaudhuri-Hocquenghem codes, is able to correct multiple errors randomly distributed in a memory chip. Using two additional bytes per 64 bits length words, this method allows to correct up to 8 bits in a memory chip that can store one byte length words.
However, as the hard failures are remaining defects, the memorization subsystem cards in which hard failures are localized need to be replaced to maintain a high availability of the memory system, i.e. to avoid memory content damages that happen when errors occur in at least two different chips of a same memorization subsystem card. In this case, the user must turn off the computer and replace the failing memorization subsystem cards. Likewise, upgrading the memory system requires to turn off the computer.
It is therefore one of the features of the present invention to provide an improved system for accessing a memory system comprising a plurality of memorization subsystems to increase the availability and the reliability of the computer(s) using such memory system.
It is another feature of the present invention to provide an improved system in which a computer memorization subsystem can be changed without disturbing the computer.
It is still another feature of the present invention to provide an improved system in which a computer memorization subsystem can be automatically replaced without disturbing the computer.
It is still another feature of the present invention to provide a method to copy and to correct the content of a memorization subsystem into another memorization subsystem.
The accomplishment of these and other related features is achieved by a system for accessing a memory device organized in a plurality of memorization subsystems for storing a plurality of data words, each data word being divided into xe2x80x9cpxe2x80x9d unitary elements. The memory device is adapted to store each of the xe2x80x9cpxe2x80x9d unitary elements into a different memorization subsystem of the plurality of memorization subsystems. The system includes an identifier for identifying at least one available memorization subsystem among a plurality of memorization subsystems, the available memorization subsystem being unused for storing any unitary elements of the plurality of data words. Further included is an insulator coupled to the plurality of memorization subsystems for individually insulating anyone of the plurality of memorization subsystems and an accessing device coupled to the identifier and to the insulator for accessing the at least one available memorization subsystem in lieu of the insulated anyone of the plurality of memorization subsystems.
The novel features believed to be characteristic of this invention are set forth in the appended claims. The invention itself, however, as well as these and other related objects and advantages thereof, will be best understood by reference to the following detailed description to be read in conjunction with the accompanying drawings.